Optimized Booth Multiplier-Based FPGA Design for Least Square Channel Estimation

Prachi Mishra; Abhishek Tomar; Prakhar Hari

Author(s)

Prachi Mishra Department of Electronics and Communication Engineering, G B P U A T Pantnagar

Abhishek Tomar Department of Electronics and Communication Engineering, G B P U A T Pantnagar

Prakhar Hari Department of Electronics and Communication Engineering, G B P U A T Pantnagar

Abstract

This paper introduces an optimized FPGA design utilizing the Booth multiplier for efficient Least Square (LS) channel estimation in wireless communication systems. A novel technique is proposed to address the worst-case scenarios associated with Booth multiplication, enhancing both robustness and efficiency in the implementation. The design is realized on the Spartan 7 FPGA platform and validated through detailed simulation waveforms, data flow designs, and schematic diagrams. Results highlight significant resource optimization, with utilization figures of just 5.59% for Slice LUTs, 0.06% for Slice Registers, and 5.00% for DSPs. The implementation achieves high processing speed and ensures reliable performance under varied operational conditions. This research provides a scalable and efficient solution for FPGA-based LS channel estimation and paves the way for future advancements in FPGAbased signal processing, potentially extending benefits to other complex applications in digital communications. The proposed design framework offers valuable insights into optimizing hardware resources while effectively handling intricate computation scenarios.

Publication Details

Page(s) 484-494

DOI DOI not available

Published Journal: International Journal of Communication Networks and Information Security, Volume: 16, Issue: S1, Year: 2024

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Keywords

Booth Multiplier, Channel Estimation, FPGA Implementation, Least Square Estimator

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