FPGA fabric specific optimization for RTL design.

Aqib Perwaiz; Hamid M.  Kamboh; Shoab A.  Khan

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FPGA fabric specific optimization for RTL design.

Author(s)

Aqib Perwaiz Computer Engineering Department, College of E&ME, National University of Sciences and Technology (NUST), Rawalpindi, Pakistan

Hamid M. Kamboh Centre for Advance Studies in Engineering, Islamabad, Pakistan

Shoab A. Khan Electrical Engineering Department, College of E&ME National University of Science and Technology (NUST), Rawalpindi)

Abstract

This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced reconfigurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned.

Publication Details

Page(s) 52-57

DOI DOI not available

Published Journal: Pakistan Journal of Engineering and Applied Sciences, Volume: 6, Issue: , Year: 2010

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