Multiplication is the basic operation in most arithmetic features in computing systems. Generally multiplier occupies large area, long delay and high power dissipation. Therefore, low power multiplier design has been an important part in very large scale integrated (VLSI) design. Power consumption is directly related to data switching patterns and it is difficult to consider high-level application-specific data characteristics in power optimization. In this paper, we present a feasible method of pipelined array multiplier and evaluated the results by the flexible estimation methods at register transfer level (RTL). The multiplier architecture is for low power and high speed applications. The experimental results indicate that the internal optimization using pipelined technique reduces the power consumption of the circuit considerably.