Sigma delta modulation based ternary FIR filter mapping on FPGA

Tayabuddin MEMON; Bhawani Shankar CHOWDHRY; Khalil ur Rahman Dayo

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Sigma delta modulation based ternary FIR filter mapping on FPGA

Author(s)

Tayabuddin MEMON School of Electrical Engineering, (RMIT), Mdbourne, AUSTRALIA

Bhawani Shankar CHOWDHRY Department of Electronic Engineering, Mehran University of Engineering & Technology, Jamshoro, PAKISTAN

Khalil ur Rahman Dayo Department of Electronic & Biomedical Engineering, Mehran University of Engineering & Technology, Jamshoro, PAKISTAN

Abstract

In this papersingle-bit SDM (Sigma Delta Modulation) based TFF(Ternary FIR Filter) with balanced ternary coefficients (i.e. -1/0/+1) has been mapped on small commercially available FPGAs (Field Programmable Gate Arrays). Filter coefficients were obtained using second order sigma delta modulator. The filter structure is based on a hierarchical adder tree that can easily be pipelined for high performance purpose. Filter structure was coded in VHDL (Very High Speed Integrated Circuit Hardware Description Language) and simulated in Quartus-I I software. The filter exhibits low I/O (Input Output) and core area usage and high performance-achieving clock speeds close to 200M Hz on a low-cost FPGA and over 500MHz on a latest FPGA commercially available device. This single-bit ternary filter is intended to support video and audio processing applications in mobile communication systems.

Publication Details

Page(s) 483-490

DOI DOI not available

Published Journal: Mehran University Research Journal of Engineering and Technology, Volume: 30, Issue: 3, Year: 2011

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