CMOS circuitry is usually associated with low power consumption, becoming the natural choice for portable, battery powered systems. It is well known that although the static power consumption is extremely low, the dynamic power consumption is approximately proportional to the operating speed. For a required data rate, the operating speeds of functional blocks within the system are dependent upon the architecture and dynamic power consumption can be very sensitive to architectural differences. Circuit level simulation of CMOS logic system, so that power consumption can be determined, is very computer intensive and usually prohibits a detailed power analysis. This paper presents methods for estimating power consumption in complex hardwired and micro coded systems on silicon.