Area efficient radix 42 64 point pipeline FFT architecture using modified CSD multiplier.

F. Siddiq; H. Jamal; T. Muhammad; M. Iqbal

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Area efficient radix 42 64 point pipeline FFT architecture using modified CSD multiplier.

Author(s)

F. Siddiq Electrical Engineering Department, University of Engineering and Technology, Taxila, Pakistan

H. Jamal Ghulam Ishaq Khan Institute of Engineering Science and Technology, Topi KPK, Pakistan

T. Muhammad Electrical Engineering Department, University of Engineering and Technology, Taxila, Pakistan

M. Iqbal Electrical Engineering Department, University of Engineering and Technology, Taxila, Pakistan

Abstract

A modified Fast Fourier Transform (FFT) based radix 42 algorithm for Orthogonal Frequency Division Multiplexing (OFDM) systems is presented. When compared with similar schemes like Canonic signed digit (CSD) Constant Multiplier, the modified CSD multiplier can provide a improvement of more than 36% in terms of multiplicative complexity. In Comparison of area being occupied the amount of full adders is reduced by 32% and amount of half adders is reduced by 42%. The modified CSD multiplier scheme is implemented on Xilinx ISE 10.1 using Spartan-III XC3S1000 FPGA as a target device. The synthesis results of modified CSD Multiplier on Xilinx show efficient Twiddle Factor ROM Design and effective area reduction in comparison to CSD constant multiplier.

Publication Details

Page(s) 345-354

DOI DOI not available

Published Journal: Nucleus, Volume: 51, Issue: 3, Year: 2014

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