High-performance optical receivers using conventional sub-micron CMOS technology for optical communication applications.

Farid. Touati; Skandar. Douss; N. Elfadil; Zia Nadir; Mohammed Bait. Suwailam; Mourad Loulou

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High-performance optical receivers using conventional sub-micron CMOS technology for optical communication applications.

Author(s)

Farid. Touati Department of Electrical and Computer Engineering, Sultan Qaboos University, Sultanate of Oman

Skandar. Douss Department of Electrical and Computer Engineering, Sultan Qaboos University, Al-Khod, Muscat, Sultanate of Oman

N. Elfadil Department of Electrical and Computer Engineering, Sultan Qaboos University, Al-Khod, Muscat, Sultanate of Oman

Zia Nadir Department of Electrical and Computer Engineering, Sultan Qaboos University, Al-Khod, Muscat, Sultanate of Oman

Mohammed Bait. Suwailam Department of Electrical and Computer Engineering, Sultan Qaboos University, Al-Khod, Muscat, Sultanate of Oman

Mourad Loulou Department of Electrical and Computer Engineering, Sultan Qaboos University, Al-Khod, Muscat, Sultanate of Oman

Abstract

A novel sub-micron total-CMOS common-gate Transimpedance Amplifier (TIA) has been designed for high-speed optical communication applications. This total-COMS approach has given a tremendous flexibility in optimizing the circuit for high performance. The new design shows superior performance compared to recent common-gate and common-base TIAs. Using conventional 0.8 um CMOS process parameters, simulations showed a transimpedance gain of 69.0dB over a 3.5 GHz bandwidth, approaching the technology fT of 10 GHz. The mean input referred noise current density was calculated to be 21.2 pA/Hz 0.5 at 3.5 GHz giving an input optical sensitivity of -20.4 dBm for a BER of 10 -9. This allows a data transmission easily at 2.5 Gbps for a NRZ synchronous link. The power consumption is only 44 m W when AC coupled to a 50 O load. In addition, the TIA was designed to tolerate a relatively wide variation in bias conditions while preserving stability. Moreover, simulations using a 0.6 um CMOS process showed even lower noise and wider bandwidth now at 6.0 GHz. The new design approaches similar IC designs in Si-bipolar or GaAs technologies. The design is the first reported TIA, which combines such features and using conventional 0.8 um CMOS transistors with fT = 10 GHz.

Publication Details

Page(s) 559-564

DOI DOI not available

Published Journal: Journal of Applied Sciences, Volume: 7, Issue: 4, Year: 2007

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