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Design OFMAC using feed forward neural networks

Author(s)
B.Divya Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Telangana, India.
Abstract
This research investigates the usage of feed forward neural networks,traditional Indian Vedic multiplier,carry skip adder,parallel in parallel out register and MAC. An Artificial Neural Network (ANN) operates in a parallel information processing structure, comprising processing units. The efficiency of the network is determined by the processing unit. Hence, there is a need to design a processing unit that is both efficient and capable of delivering superior performance. This processing unit encompasses a MAC unit (Multiplication and Accumulation) and an Activation unit. The main focus of high-speed processors is to minimize power consumption and processing times. The implementation of the design utilizes Verilog, a hardware description language, and the testing phase is carried out using the Modelism simulator.The study performance the 4 bit mac using feed forward network with 4 bit mac using logic gates.
Publication Details
Page(s) 1062-1068
DOI DOI not available
Published Journal: International Journal of Communication Networks and Information Security, Volume: 16, Issue: 4, Year: 2024

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Keywords
MAC, Artificial Neural Network, Vedic Multiplier, carry skip adder and Verilog HDL
References
. .Energy-efficient neural network design using memristive MAC unit" by Frontiers - This paper describes a novel MAC unit based on mixed-signal multipliers using transistor-memristor cells on crossbar intersections, focusing on energy-efficient neural network design.. , : .
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. .Design of MAC unit in artificial neural network architecture using Verilog" by IEEE - This paper discusses the design of MAC units in ANN architectures using Verilog HDL. , : .
Dynamic MAC . .-based architecture of artificial neural networks suitable for hardware implementation on FPGAs" - This study presents a dynamic MAC based architecture for ANNs that is suitable for hardware implementation on Field-Programmable Gate Arrays. , : .
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