Optimizing CMOS circuits for performance improvements using adiabatic logic.

P. Vijayakumar; M Shanthanalakshmi; K Gunavathi

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Optimizing CMOS circuits for performance improvements using adiabatic logic.

Author(s)

P. Vijayakumar Department of Electrical and Electronics, PSG College of Technology, Coimbaore, India

M Shanthanalakshmi Department of Electronics and Communication, PSG College of Technology, Coimbatore, India

K Gunavathi Department of Electronics and Communication, PSG College of Technology, Coimbatore, India

Abstract

Retiming is an efficient technique for redistributing latches in circuits in order to improve the circuit performance. However the retiming inherently increases the power dissipation because of the inclusion of latches for pipelining the circuit. We present an efficient Improved Positive Feedback Adiabatic Logic (IPFAL), which utilizes the inherent nature of pipelining in the circuits with the help of four-phase power clock. The IPFAL efficiently recovers the stored charge from the load capacitance and hence reduces the non-adiabatic losses in the circuits. The proposed technique is validated by applying it to a number of ISCAS benchmark circuits and the results are compared with those of the pipelined circuits with retiming algorithm. The experimental results prove that the circuits implemented in IPFAL has a maximum reduction in power dissipation of up to 89% when compared to the ones using retiming algorithm.

Publication Details

Page(s) 325-331

DOI DOI not available

Published Journal: Information technology Journal, Volume: 6, Issue: 3, Year: 2007

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