FPGA implementation of Antilogarithmic computation using Fixed point Architecture at SoC Integration

Chaya Bhavi; Anuradha M. Sandi

Author(s)

Chaya Bhavi Department of Electrical Science, Guru Nanak Dev. Engineering College and Visvesvaraya Technological University Belagavi-590018,Karnataka,India

Anuradha M. Sandi Department of Electronics & Communication, Guru Nanak Dev. Engineering College and Visvesvaraya Technological University Belagavi-590018,Karnataka,India

Abstract

In recent research works in System on Chip (SoC) and Embedded systems applications demands optimization of power, latency, area and improvement of throughput. All these applications are complex in operations and to validate FPGA is best suitable device with minimal time. Most of operations in DSP applications uses fixed point and data path are widely used and realization of complex arithmetic operations using logarithmic number systems. In order to improve throughput and optimize power, area and delay, a novel antilogarithmic architecture has been realized on FPGA. The proposed antilogarithmic function uses piecewise linear approximation (PLA), Leading one detector (LoD), barrel shifter (BS) and Reconfigurable residue number system (RRNS), Parallel Prefix Adder (PPA) are incorporated in the design. The SoC level design has been synthesized in Vivado Design Suite 2018.1 and validated on Artix-7 FPGA. The device utilization demonstrates how little FPGA resource the architecture uses. Additionally, we have examined the approximation result through error analysis. According to the error study, there is a 2.4% mistake for negative numbers and a 0.24 % error for positive values. By using more bits for the fractional bit representation, the inaccuracy can be reduced even more.device. The device utilization demonstrates optimal latency and minimal logic resources, and the same design is validated on the FPGA. Additionally, we have examined the approximation result through error analysis. The LOD designs and an approximation adder for summing two logarithms that can be applied to enhance the Mitchell logarithmic (ML) multiplier's hardware efficiency.In comparison to the original Mitchell multiplier, this design lowers hardware costs by 21.8%, while in comparison to the other current iteration, it lowers costs by 17.5%.The'm' least significant bits of the approximation adder have a fixed bias has ones and zeros. In order to minimize hardware costs and maintain the complete accuracy of the traditional ML, the ideal values for "b" and "m" are selected. Based on an overall examination of errors, the error for positive numbers is 0.9%, while the error for negative numbers is 0.5%. By using more bits for the fractional bit representation, the inaccuracy can be reduced even more..

Publication Details

Page(s) 1122-1132

DOI DOI not available

Published Journal: International Journal of Communication Networks and Information Security, Volume: 16, Issue: S1, Year: 2024

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Keywords

Mitchell logarithmic fixed-point architecture, approximate adder, Antilogarithm, leading one detector, multiplier and FPGA.

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