Hardware implementation method of secret data security on FPGA based on zig-zag map encryption and stegano algorithms

BAYU KUMORO YAKTI; SUNNY ARIEF SUDIRO; SARIFUDDIN MADENDA; SURYADI HARMANTO

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Hardware implementation method of secret data security on FPGA based on zig-zag map encryption and stegano algorithms

Author(s)

BAYU KUMORO YAKTI Doctoral Program in Information Technology Gunadarma University, Jakarta – Indonesia

SUNNY ARIEF SUDIRO Sekolah Tinggi Manajemen Informatika dan Komputer Jakarta STI&K, Jakarta – Indonesia

SARIFUDDIN MADENDA Doctoral Program in Information Technology Gunadarma University, Jakarta – Indonesia

SURYADI HARMANTO Doctoral Program in Information Technology Gunadarma University, Jakarta – Indonesia

Abstract

The internet has grown so rapidly that most of the individuals prefer to use the internet as the main medium for transferring data. Data protection is very important especially when sending secret data from one place to another. This paper proposes a zig-zag mapping transposition encryption-decryption algorithms and Least Significant Bit (LSB) steganography algorithm for data security improvement. The hardware implementation methods of these algorithms into Field Programmable Gate Array (FPGA) for data protection in real-time communication are also offered. The FPGA Intellectual Property core (IP core) resulting employed minimal LUTs resources. The encryption and steganography algorithms occupy 107 LUTs and take 1.821 ns for each 64 bits data processing. Whereas steganalysis and decryption algorithms needed108 LUTs and 2.172 ns processing time.

Publication Details

Page(s) 5572-5582

DOI DOI not available

Published Journal: Journal of Theoretical and Applied Information Technology, Volume: 100, Issue: 17, Year: 2022

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Keywords

LUTs FPGA resources, Zig-zag Mapping Transposition, Encryption-decryption, LSB steganography

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