A rapid growth in digital signal processing applications has increased the requirement for high-speed digital systems. Multiprocessor systems are the best choice for these applications. A prior sequence of operations should be applied to the operations that describe the nature of these applications before hardware implementation is produced. These operations should be time scheduled and hardware allocated. This paper proposes a new scheduling technique for digital signal processing (DSP) applications that are represented by data flow graphs (DFGs). In addition, hardware allocation is implemented in the form of embedded system. The proposed scheduling technique also achieves the optimal scheduling of a DFG at design time. The optimality criterion considered in this algorithm is the maximum throughput within the available hardware resources. The hardware system is composed of one or multiple homogenous pipelined processing elements and designed to meet the maximum-rate schedule. Two implementations are proposed of the system architecture according to the number of the processing elements. These are the serial system and the parallel system. The serial system comprises one processing element where all tasks are processed sequentially. On the other hand, the parallel system has four processing elements to execute tasks concurrently. The hardware systems have been described, functionally tested, and synthesized using the Verilog HDL and Xilinx ISE. Synthesis results show that the parallel system outperforms the serial one by 25.5% in terms of performance with extra area penalty. The relationship between the number of instructions that are executed in both systems, the system area, and the system performance as represented by the system frequency, have been studied. The proposed scheduling technique is shown to outperform the retiming technique, which we have chosen to compare with. The serial system has better performance with 19.3% higher system frequency than that of the retiming technique. The parallel system also outperforms the retiming technique in terms of the system frequency by 51.2%.