Now, header parsing is the main topic in the modern network systems to support many operations such as packet processing and security functions. The header parser design significantly affects the network devices' performances (latency, throughput, and resource utilization). However, the header parser design suffers from many difficulties, such as the incrementing in network throughput and various protocols. Therefore, the programmable hardware packet parsing is the best solution to meet the dynamic reconfiguration and speed needs. Field Programmable Gate Array (FPGA) is an appropriate device for programmable high-speed packet implementation. Most high-speed programmable packet systems use the P4 language (Programming protocolindependent Packet Processors) because it is a high-level abstract description language. This paper introduces a novel FPGA HighPerformance Programmable Packet Parser architecture (HP4). HP4 is automatically generated by the generating unit (convert P4 programs to VHDL code) to optimize the speed, dynamic reconfiguration, and resource consumption. The HP4 shows a pipelined packet parser dynamic reconfiguration and low latency. In addition to high throughput (over 600 Gb/s), HP4 resource utilization is less than 7.5 percent of Virtex-7 870HT, and latency is about 88 ns. High-speed dynamic packet switch and network security can use HP4.