In this paper, a power macro-modelling technique at register transfer level (RTL) for the digital electronic systems composed of intellectual property (IP) components by using the statistical knowledge of their primary inputs/output is presented. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate the power dissipation of the system just by using the statistics of the IPs primary inputs/outputs. In the correct work with the test IP system, the average error is 26%.