4x4 Bit Multiplier Designs using Different CMOS Schematics, and their Comparison | Technical Journal 2019

Author(s)

K.rana Chung-Ang University, Seoul, Republic of Korea

A.Niaz HITEC University, Taxila, Pakistan

S.Hanif HITEC University, Taxila, Pakistan

M.T.Ali HITEC University, Taxila, Pakistan

Abstract

In this paper, low power and high speed 4x4 bit multipliers are presented. The full adder and a half adder blocks used in these multipliers are designed using adiabatic and transmission gate techniques respectively. The multiplier circuit is implemented using Dadda algorithm. This circuit is simulated in 1P9M Low-K UMC 90nm CMMOS process technology (cadence Virtuoso). The circuit operates at clock frequency of 5.46 and 8.54 GHz and dynamic average power of 2.667 and 1.139 mW respectively, at room temperature of 27°C and 1.9V supply voltage.

Publication Details

Page(s) 15-22

DOI DOI not available

Published Journal: Technical Journal, Volume: 24, Issue: 4, Year: 2019

Keywords

Dadda Tree Reduction Algorithm 4x4 bit Multiplier Adiabatic logic Transmission gate logic

References

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Citations

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