A multi-FPGA rapid prototyping system with the reusable AES core. | [Information technology Journal • 2005]

Author(s):

1. Fang-Hsi Kuo: Department of Information Management, Jin Wen Institute of Technology, Taiwan, Republic of China

2. Shou-Te Yen: Computer System Laboratory, Department of Information Engineering and Computer Science, Feng Chia University, Taiwan, Republic of China

3. Chia-Cheng Liu: Computer System Laboratory, Department of Information Engineering and Computer Science, Feng Chia University, Taiwan, Republic of China

Abstract:

In this study authors developed a reconfigurable rapid prototyping system with PCI as interface. Reconfigurable processing unit uses I/O coupling way with general propose processor to work in coordination and to accelerate the execution of the specific task. Use four FPGA chip in order to offer the hardware design environment under multi-FPGA structures systematically at the same time. This system except that the intact hardware is designed and implemented, but also include the setting-up of the driver with offer the application program interface which access the hardware. In order to prove that systematic function of rapid prototyping board is correct, design one IP core apply to this system. Authors implemented an Advanced Encryption Standard (AES) hardware circuit for this goal. The focal point designed lies in making optimization to resources of FPGA and AES suitability in reconfigurable computing with multi-FPGA system.

Page(s): 262-270

DOI: DOI not available

Published: Journal: Information technology Journal, Volume: 4, Issue: 3, Year: 2005

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