Author(s):
1. Tran Sy Nam:
Institute of Cryptographic Science and Technology, Vietnam Government Information Security Committee,,Vietnam
2. Hoang Van Thuc:
Institute of Cryptographic Science and Technology, Vietnam Government Information Security Committee,,Vietnam
3. Nguyen Van Long:
Institute of Cryptographic Science and Technology, Vietnam Government Information Security Committee,,Vietnam
Abstract:
In this paper, we present a high-throughput FPGA implementation of IPSec core. The core supports both NAT and non-NAT mode and can be used in high-speed security gateway devices. Although IPSec ESP is very computing intensive for its cryptography process, our implementation shows that it can achieve high throughput and low lantency. The system is realized on the Zynq XC7Z045 from Xilinx and was verified and tested in practice. Results show that the design can gives a peak throughput of 5.721 Gbps for the IPSec ESP tunnel mode in NAT mode and 7.753 Gbps in non-NAT mode using one single AES encrypt core. We also compare the performance of the core when running in other mode of encryption.
Page(s):
43-50
DOI:
DOI not available
Published:
Journal: International Journal of Communication Networks and Information Security, Volume: 14, Issue: 1, Year: 2022
Keywords:
ESP
,
NAT
,
FPGA
,
Zynq
,
IPSEC
,
IKE
References:
References are not available for this document.
Citations
Citations are not available for this document.