Abstract:
The authors propose a 32x32-bit multiplier with reduced delay compared to conventional multiplication algorithms. An efficient radix-2 recording logic generates the partial products. A 2-phase micro pipeline latch controller is used which controls a 4-phase pipeline with standard transparent level sensitive latches. The design employs the modified Booth algorithm diminishing 8 bits at a time with an iterative structure. Assign extension algorithm is also employed in this study. Furthermore, the early termination scheme speeds up the multiplication operation. The multiplication time is 3.1 n sec at a 1.3-v power supply. Present multiplication algorithm showed 13% speed improvement, 14% power savings and 905% reduction in transistor count when compared to the conventional multiplication algorithms.
Page(s):
2629-2634
DOI:
DOI not available
Published:
Journal: Journal of Applied Sciences, Volume: 7, Issue: 18, Year: 2007