Abstract:
In this paper the authors propose an efficient architecture for the implementation of a LVQ (Learning Vector Quantization) NN (Neural Network), used as a classifier, for PAPR (Peak to Average Power Ratio) reduction. A special feature of the implementation is a combinatorial module for nearest neighbor search that allows online execution of this important operation during classification. The LVQ classifier is programmed in Verilog and the entire circuit is synthesized on FPGAs (Field Programmable Gate Arrays) using Xilinx(R) ISE (Integrated Software Environment) 8.li. The model is implemented with 64 sub carriers, considering the parametric values of WLANs standard IEEE 802.11a. Using the architecture, efficient on-line classification is achieved.
Page(s):
79-88
DOI:
DOI not available
Published:
Journal: Mehran University Research Journal of Engineering and Technology, Volume: 29, Issue: 1, Year: 2010