Abstract:
This article focuses on Trace Back Unit of Viterbi algorithm for constraint length K=7. Conventional Trace Back Unit comprises of three types of Memory operations: decision bits write, trace back read & decode read whereas the Pre-Trace Back approach exploits the inherent parallelism between the decision bits write & decode traceback operation. This approach results in reduction in latency & hardware. In this article, the implementation of Trace Back Unit using Pre-Traceback approach is presented. The design has been implemented using high-level Verilog HDL and functionally verified by mapping on to Xilinx Virtex2P FPGA.
Page(s):
27-30
DOI:
DOI not available
Published:
Journal: Proceedings 5th International Bhurban Conference on Applied Sciences and Technology , Volume: 0, Issue: 0, Year: 2007