Abstract:
This paper describes the VLSI architecture of deblocking filter, which is a part of H. 263+ video codec. H. 263+ is ITU-T standard defined in 1998, with 12 modes, which are divided in three levels and deblocking filter is placed in level one. H. 263 is block based coding scheme, which results in block noise and artifacts produces during coding process. The main purpose of proposed filter module is to reduce the artifacts produced by blocking noise. Proposed architecture reduces the hardware cost by reusing the intermediate results and computations efficiently. Furthermore a new proposed scheme for filter memory reduces the overhead for DMA access and also results in significant reduction of filter memory size. Implementation results are shown to demonstrate that filter module can be implemented by adding small area to the baseline H. 263 codec core.
Page(s):
105-110
DOI:
DOI not available
Published:
Journal: Journal of Engineering and Applied Sciences, Volume: 25, Issue: 1, Year: 2006